analog power AM20P06-90D p-channel 60-v (d-s) mosfet v ds (v) i d (a) -20 -18 symbol limit units v ds -60 v gs 20 continuous drain current a t c =25c i d -20 i dm -80 i s -20 a power dissipation a t c =25c p d 50 w t j , t stg -55 to 175 c symbol maximum units r ja 40 r jc 3 notes a. surface mounted on 1 x 1 fr4 board. b. pulse width limited by maximum junction temperature pulsed drain current b continuous source current (diode conduction) a thermal resistance ratings c/w parameter operating junction and storage temperature range absolute maximum ratings (t a = 25c unless otherwise noted) v parameter drain-source voltage gate-source voltage product summary -60 r ds(on) (m) 90 @ v gs = -10v 108 @ v gs = -4.5v a maximum junction-to-ambient a maximum junction-to-case key features: ? low r ds(on) trench technology ? low thermal impedance ? fast switching speed typical applications: ? load switches ? dc/dc conversion ? motor drives ? preliminary 1 publication order number: ds_AM20P06-90D_1a
analog power AM20P06-90D parameter symbol test conditions min typ max unit gate-source threshold voltage v gs(th) v ds = v gs , i d = -250 ua -1 v gate-body leakage i gss v ds = 0 v, v gs = 20 v 100 na v ds = -48 v, v gs = 0 v -1 v ds = -48 v, v gs = 0 v, t j = 55c -10 on-state drain current a i d(on) v ds = -5 v, v gs = -10 v -30 a v gs = -10 v, i d = -10 a 90 v gs = -4.5 v, i d = -8 a 108 forward transconductance a g fs v ds = -15 v, i d = -10 a 10 s diode forward voltage a v sd i s = -10 a, v gs = 0 v -1 v total gate charge q g 10 gate-source charge q gs 4.0 gate-drain charge q gd 3.3 turn-on delay time t d(on) 6 rise time t r 5 turn-off delay time t d(off) 38 fall time t f 14 input capacitance c iss 1142 output capacitance c oss 84 reverse transfer capacitance c rss 59 notes a. pulse test: pw <= 300us duty cycle <= 2%. b. guaranteed by design, not subject to production testing. dynamic b ns static ua electrical characteristics i dss m r ds(on) nc v ds = -30 v, r l = 3 , i d = -10 a, v gen = -10 v, r gen = 6 v ds = -30 v, v gs = -4.5 v, i d = -10 a drain-source on-resistance a zero gate voltage drain current analog power (apl) reserves the right to make changes without further notice to any products herein. apl makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does apl assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in apl data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customers technical experts. apl does not convey any license under its patent rights nor the rights of others. apl products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the apl product could create a situation where personal injury or death may occur. should buyer purchase or use apl products for any such unintended or unauthorized application, buyer shall indemnify and hold apl and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that apl was negligent regarding the design or manufacture of the part. apl is an equal opportunity/affirmative action employer. pf v ds = -15 v, v gs = 0 v, f = 1 mhz ? preliminary 2 publication order number: ds_AM20P06-90D_1a
analog power AM20P06-90D 1. on-resistance vs. drain current 2. transfer characteristics 3. on-resistance vs. gate-to-source voltage 4. drain-to-source forward voltage 5. output characteristics 6. capacitance typical electrical characteristics 0 0.05 0.1 0.15 0.2 0 1 2 3 4 5 rds(on) - on - resistance( ) id - drain current (a) 3.5v 4.5v,6v,8v,10v 4v 0 1 2 3 4 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 id - drain current (a) vds - drain - to - source voltage (v) 10v,8v,6v,4.5v 4v 3.5v 0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 rds(on) - on - resistance( ) vgs - gate - to - source voltage (v) tj = 25 c tj = 25 c 0 1 2 3 4 5 0 1 2 3 4 5 id - drain current (a) vgs - gate - to - source voltage (v) tj = 25 c 0.01 0.1 1 10 0.2 0.4 0.6 0.8 1 1.2 is - source current (a) vsd - source - to - drain voltage (v) tj = 25 c 0 200 400 600 800 1000 1200 1400 1600 0 5 10 15 20 capacitance (pf) vds - drain - to - source voltage (v) ciss coss crss f = 1mhz id = - 10a ? preliminary 3 publication order number: ds_AM20P06-90D_1a
analog power AM20P06-90D 7. gate charge 9. safe operating area 10. single pulse maximum power dissipation 8. normalized on-resistance vs junction temperature 11. normalized thermal transient junction to ambient typical electrical characteristics 0 2 4 6 8 10 0 10 20 30 vgs - gate - to - source voltage (v) qg - total gate charge (nc) 0.01 0.1 1 10 100 1000 0.1 1 10 100 1000 id current (a) vds drain to source voltage (v) 10 us 100 us 1 ms 10 ms 100 ms 1 sec 10 sec 100 sec dc idm limit limited by rds 1 0 20 40 60 0.001 0.01 0.1 1 10 100 1000 peak transient power (w) t1 time (sec) 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t1 time (sec) d = 0.5 0.2 0.1 0.05 0.02 single pulse r ja (t) = r(t) + r ja t j - t a = p * r ja (t) duty cycle, d = t 1 / t 2 0.5 1 1.5 2 -50 -25 0 25 50 75 100 125 150 rds(on) - on - resistance( ) (normalized) tj - junctiontemperature( c) p(pk) t 1 t 2 r ja = 40 c /w vds = - 30v id = - 10a ? preliminary 4 publication order number: ds_AM20P06-90D_1a
analog power AM20P06-90D package information note: 1. all dimension are in mm. 2. package body sizes exclude mold flash, protrusion or gate burrs. mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 3. package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. ? preliminary 5 publication order number: ds_AM20P06-90D_1a
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